Analysis of an Area Efficient Vlsi Architecture for Floating Point Multiplier and Galois Field Multiplier*

This article deals with the VLSI architecture of the Floating point and Galois field multiplier, using a technique called Wave-pipelining. Wave -pipelining is a circuit design technique that allows digital synchronous systems to be clocked at rates higher than conventional pipelining techniques. Wave pipelining can improve the throughput of a logic circuit while avoiding some of the overheads of traditional pipelining. Multiplication plays a very important role in the signal processing applications. In the VLSI platform, the area consumption is judged with the number of gates required to realize the logic. Accordingly, the multiplier structures, which we have traditionally, are computation intensive thereby involves larger usage of flipflops and slices in terms of architecture realization. To reduce the area consumption, the technique of wave pipelining has been incorporated, which also paves way for the low power architecture. The concept has been verified with the other kind of multiplier namely, Galois field multiplier, which has its existence in coding theory and cryptography analysis. The analysis of the designed architectures is done in Xilinx and Synopsys, targeted to 90nm technology.